As mentioned briefly in my previous post, Moore’s law is not merely about the number of transistors integrated into a small chip. It is generally about strategies to decrease the processing time, power consumption, weight and cost (have a look at the new Skylake processor for example). Although with the recent IBM’s announcement of 7nm chip technology, increasing computing power through increasing transistors count still seem to be the main preference for industries, they have been continuously looking into alternatives as the current silicon technology is approaching its limits. In bypassing those limits, materials engineering has done a great deal of benefit and will continue to play a significant role in the future. In what follows, I will go briefly through materials engineering related strategies applied to keep up the pace of development Moore predicted 50 years ago.
Late 90s was the time when microelectronic industries realised the urge for switching from aluminium to copper interconnect. This was basically due to higher conductivity of copper compared to aluminium leading to less power consumption and smaller metallic components. Additionally, higher resistance of copper to electromigration was another advantage which appeared attractive to the industry. Electromigration is a phenomenon through which mass of atoms are misplaced due to collision of the current conduction electrons with the atoms. This misplacement of atoms is highly undesirable in terms of reliability of electronic devices. Material chemistry and microstructure of material such as grain size and orientation can play a significant role in electromigration of atoms. However apart from metallurgical factors, current density is a major role player and it can highly aggravate the effect of electromigration. As the current density in the interconnect is high enough to aggravate electromigration, therefore it is a serious reliability problem and copper has remained the metal of choice for interconnect materials.
Gate leakage in semiconductor devices is a quantum mechanics phenomenon through which mobile charge carriers tunnel through an insulating barrier. Gate leakage is very sensitive to the thickness of insulating barriers and obviously highly undesirable as it reduces the processor performance quite significantly. Minimizing leakage is necessary to facilitate miniaturization of electronic devices and one way to reduce leakage could be increasing thickness, however, it should be noted that increasing physical thickness which leads to an increased electrical thickness is not an option as it deteriorates transistors performance. Apart from proper system design which I don’t want to go through that here, it appeared that with a proper selection of materials it is possible to further down scale the electrical thickness while providing a physically thicker layer, achieved by replacing silicon dioxide with high dielectric constant metal oxides (so called high-k dielectric). Hafnium-based dielectric layer in combination with a gate electrode composed of alternative metal materials was Intel’s ingredient for fabrication of 45 nm microprocessors in 2007 and the following down scaling of transistors beyond 45 nm.
Another way to improve the performance of transistors and speed up the processing time is increasing the electron mobility through changing silicon properties. Stretching atoms of silicon beyond their normal interatomic distance decreases the forces that interfere with the movement of electrons leading to a boost in the performance of a transistor. Strained silicon technology is currently using the same concept to increase the electron mobility of silicon which is done through depositing a layer of silicon on the top of silicon-germanium layer. Due to a mismatch between the atoms of silicon layer and silicon-germanium layer, the atoms of silicon are stretched. The force stretched atoms apply on the moving electrons is reduced notably, thereby enhancing electron mobility of silicon compared with normal bulk silicon crystal.
Materials with higher electron mobility than silicon
In my twitter feed yesterday there was an announcement from Intel regarding its new $50M investment in quantum computing. Whenever I hear about quantum computing, the first thing that comes automatically to my mind as a materials engineer is the destiny of current established and future developing materials (for the purpose of computing) with the advent of quantum computing. I have not done much research into quantum computing yet but up to my limited understanding, silicon’s related limitations does not apply in quantum computing. This means that with quantum computing silicon would remain material of choice without the requirement of replacing it with new exotic materials. However, it seems that quantum computing has got a long way to go and replacing silicon seem to be a more tangible option to catch up with Moore’s prediction.
For instance, a new family of semiconductors, so called compound semiconductors (they are composed of two or more elements such as indium arsenide and indium antimonide), have electron mobility up to 50 times higher than silicon and their application is in the rise. In addition, adding a small amount of germanium to silicon can enhance its electron mobility properties and this approach is also in use already. It is interesting to note that very first semiconductor devices were made of germanium so moving back to a fully germanium chip could be a possible option. Moreover, hybrid semiconductors in which different materials are combined could be a real life possibility anytime soon.
Graphene or the “miracle material” has been attracting a lot of attention recently as a possible alternative to silicon due to its extraordinary properties such as remarkable strength, thermal and electrical conductivity. In its current form however, graphene is not viable as a semiconductor material because it lacks a band gap which is a requirement for semiconducting properties. If the issue of lack of band gap is resolved, then graphene could be a promising future material for further development of electronic devices. Carbone nanotube is another form of graphene (rolled graphene) which holds promises as possible future material for microelectronic industry. Similarly, it has extraordinary properties in terms of strength, electrical and thermal conductivity, however, the current challenges with manufacturing of carbon nanotube such as control over diameter, density and chirality remain the main barrier against its commercial applications.
moving up from chip level to assembly of components level, there are still more room for materials engineering and specifically metallurgy to play a role in keeping up with Moore’s prediction – which I will go through that in a separate post. Stay tuned!