Development in electronic packaging and their reliability concerns from metallurgical perspective: part I


If you are interested in microelectronics industry and are following the latest trends, you have heard the buzz about internet of things (IoT) and wearable technology. Although the concept might not be new, the advances in microelectronics now allow smooth adoption of the technology, revolutionizing human’s life once again after the arrival of internet. In this regard, advanced electronic packaging is a key component to successful integration of IoT and wearable technology. Generally, the essence in advanced electronic packaging is integrating multifunctional modules (logic, memory, RF, sensors, etc.) based on 3D integration. 3D integrated circuits (3D ICs) requires an increased Input/Output densities, stacking chips and interconnecting vertically by through silicon via (TSV) technology providing high performance, low power and reliable electronics. However to the best of my knowledge, moving toward 3D ICs does not exempt from complications and a lot of effort is going on in the industry to overcome those complications. Many of these challenges originates from the fact that despite significant experience of industry in 2D flip chip packaging technology, many of those experiences are not transferable to 3D packaging. This is while as the chip technology is approaching the limits of Moore’s law, moving to 3D ICs seems inevitable as it offers ample room for further growth of electronic industry for at least the next 15-20 years.

Generally, a chip contains different metallic components and understanding metallurgical principles governing the behavior and reliability of these components appears vital to further development of the technology. In metallurgical science, size effect is always a concern as reducing the size (of grains, thickness, precipitates, etc) below a certain amount can potentially alter the governing metallurgical principles. For instance, when the grain size is reduced to the range of nanometers dislocation mediated mechanisms will be largely replaced by grain boundary mediated mechanisms. These change of mechanisms are the origin of complications associated with materials behavior when reducing size is inevitable.  As already mentioned, the new trend in electronic packaging is all about miniaturising and reducing sizes.  Likewise, the well-known metallurgical principles which formed the foundation of reliability experience of the industry for years , changes with this emerging trend of miniaturizing and a new level of understanding is required to keep up with the demand of the market. As an example of this, moving from 2D ICs to 3D ICs requires a significant reduction in the size of bumps to the range of so-called micro-bumps. This continuous reduction in size of bumps can eventually reach to the point where each micro-bump contains only one single grain leading to a significant inhomogeneous behavior across the entire 3D ICs, as each single grain can respond to its environment differently based on its orientation.   In this (and following) post, thus, I aim to provide an overview of the current trend in electronic packaging and relevant reliability issues from metallurgical perspective.


TSV and Micro-bumps the main metallic (and the most mischievous) components of 3D ICs

More dense, high performance 3D ICs requires an increasing number of Inputs/Outputs (IOs) obtained through scaling down to fine pitch and micro-bumps less than 50 micron and stacking multifunctional chips (such as logic, memory, RF and MEMS) using TSV interconnect. TSV interconnect are copper vias in polycrystalline form vertically passing through chips providing connection between chips. TSVs are created through a process of etching and electroplating. In this process through holes are etched which are then filled with electroplated copper. The main advantage of TSV is the reduced travel length of signal from one layer to another, allowing an increased interconnect density, therefore increased functionality and performance. The connection between vertical vias in different layer is made through micro-bump technology. Micro-bumps are created by means of electroplating process. As mentioned earlier, due to the compact nature of 3D IC, micro-bumps used in this technology are much smaller than the conventional bump size used in 2D packaging. The thermal mismatch of the components (e.g. difference in coefficient of thermal expansion of TSV copper and silicon) and the small size of micro-bumps leads to some unique characteristics that can create some critical reliability issues (when I was first learning about micro-bumps and TSVs, the first thing that passed my mind was how mischievous these components are as I never knew how much trouble they can create in advanced electronic packaging). In what follows in this part, I try to cover micro-bumps and their reliability concerns briefly and TSVs will be reviewed in a separate post. Please keep in mind that the universe of metallurgy of microelectronics is vast and what is provided here is just a brief summary of the literature.


Microbumps and Intermetallic Compounds Formation

Soldering is the essential part of interconnection technology and obviously will remain so in the future. By definition, soldering is the chemical reaction between the solder alloy and the two surfaces to be joined together. Since 2006, the consumer electronic market has fully transferred to Pb-free solder alloys due to the health and environmental concerns associated with Pb-Sn solder alloys. Replacement of Pb-Sn was initially appeared possible through a near eutectic Sn-Ag-Cu or SAC alloy. However, development of SAC alloys did not lead to a stop to further alloy developments and there has been continuous effort to develop solder alloys for a wide range of applications. Nevertheless, since near eutectic SAC alloy is the most common solder alloy currently and it is believed that it will remain to be the major candidate for 3D ICs, at least in the near future, the information is provided in this post is mainly based on this alloy.

Generally, an interconnect system consists of solder bumps in contact with under bump metallurgy system or UBM. UBM to interconnection technology is like a foundation to a house providing support to the whole system. UBM contains different metallic layers (or thin films) each playing different role. In case of SAC solder alloy, the UBM is composed of a Cu layer as solder adhesion layer, Ni layer as the diffusion barrier layer and Au layer as the oxidizing barrier layer. Cu, Ni, Ag, and Au are known as fast diffusers meaning that their diffusion rate in body centred tetragonal Sn is orders of magnitude higher than self-diffusion rate of Sn [1]. Therefore, the interfacial chemical reaction between solder and UMB leads to formation of IMCs which is on one hand an indication of a good metallurgical bonding, but on the other hand IMCs are brittle in nature and prone to structural defects which can undermine the reliability of solder joints.

The intermetallic product of reaction between solder alloy and UBM varies depending on the solder alloy composition, UBM layer components, UBM layer thickness and kinetics of reaction. In a binary system possible alternatives of IMCs are as follow: Cu6Sn5, Ni3Sn4 and AuSn4. However, through multiple reflow and subsequent aging treatment Cu3Sn [2] and other alternatives of ternary and quaternary IMCs appears in the solder [3, 4]. Cu3Sn formation is accompanied by Kirkendall voids formation, a phenomena resulted from the difference between the diffusion rates of Cu and Sn which promotes voids formation and eventually crack formation at the interface of Cu3Sn and Cu [5].

In the conventional flip chip with bump sizes of larger than 50μm, IMCs can form both as a thin layer at the interface and as particles distributed in the matrix of solder depending on the type of IMCs formed. A thin layer of IMC at the interface provides a good bonding and dispersed IMC particles in the matrix can improve mechanical properties of the joints. However in 3D IC technology with the micro-bump size requirements in the range of a few micrometers, solder alloy can potentially turn fully into IMCs that  is not regarded beneficial in terms of mechanical properties of the joints (due to their brittle nature). Another example of complications associated with the small volume of micro-bumps is formation of Ag3Sn (another form of IMCs).  While Ag3Sn does not seem to be much of a concern in conventional flip chip bump sizes, it can create serious reliability concerns in micro-bumps [6, 7]. The reason for formation of Ag3Sn in microbumps originates from the low volume of solder alloy in micro-bump. Rapid initial consumption of Sn by IMC formation leads to an increase in concentration of Ag which in turn promotes Ag3Sn formation [6].

Other than being brittle, different IMCs have different thermal expansion leading to formation and propagation of voids at the interface of IMCs in the subsequent aging treatments [8, 9]. Similar to Kirkendall voids, these voids can lead to crack propagation and early failure of the interconnect thereby, creating a significant reliability issue in micro-bumps where a large fraction of solder alloy transforms to IMCs.

As a large fraction of micro-bumos turn into IMCs during subsequent thermal treatment, It should be ,therefore, noted that the reliability standards developed for conventional flip chip bumps could not be transferred to micro-bumps as the reliability of the former is dominated by properties of βSn while the latter is dominated by IMCs. Surely, developing new reliability standards is an exciting field of work from my perspective as a scientist but a tough challenge for industry in the effort to track I/O roadmap.


Micro-bumps and Electromigrations

Electromigration (EM) refers to the mass transport of atoms under applying current density in metals. The flux of atoms in the direction of electron flow leads to fast dissolution of UBM and voids/hillocks formation at the interface of joint and UBM. The former increase the rate of IMCs formation and the latter leads to an increase in current crowding effect and further elevating EM. Extensive IMC formation and voids at the interface can create localized stress concentration while in service resulting in early failure of electronic components and devices.

The smaller size of micro-bumps results in substantial increase of current density flowing through the joints based on this relation:


Where J is the current density, I is the current and A the area. For example, applying a current of 0.05A on a 20μm-microbump results in a value in order of 104A/cm. Increasing current density increases the transport of Cu, Ni, Au and Ag atoms driven by electron current. Additionally, increasing current density leads to a local increase of joint temperature as Joule heating is proportional to the square of current density. Also, field service temperature can reach as high as 100 °C, approximately 76% of the melting temperatures of SAC alloy. High current density and high temperature in the micro-bumps, therefore, promotes the flux of atoms and increase the diffusion rate in the direction of electron flow. Consequently, EM could be significantly pronounced reliability issue in 3D ICs technology with an enhanced rate of IMCs and Kirkendall voids formation, if compared with conventional flip chip technology under the same applying current. However, it is interesting to note that there are evidence of an improved resistance to EM in 3D ICs and that is attributed to fact that IMCs have an enhanced resistance to EM in comparison with the solder alloy [10, 11]. Once the solder alloy transformed fully or largely to IMCs, therefore, a drop in EM rate is expected.


Micro-bumps and microstructural anisotropy

Micro-bumps can have dimensions one to two orders of magnitude smaller than the conventional bumps in the flip-chip technology. This significant reduction in dimension may result in micro-bump having only one grain. As Sn has a body-centered tetragonal crystal structure, its properties (e.g. conductivity) is anisotropic. Even when micro-bumps are fully consumed by ICs, not much changes are expected in terms of isotropic properties as crystalline structure of ICs are mainly anisotropic, as well [12,13]. This would be a serious reliability concern when there are a large number of micro-bumps.


[1] M. Lu, D.-Y. Shih, P. Lauro, C. Goldsmith, D.W. Henderson, Applied Physics Letters, 92 (2008) 211909.

[2] T. Laurila, V. Vuorinen, J.K. Kivilahti, Materials Science and Engineering R: Reports, 49 (2005) 1.

[3] C.E. Ho, W.T. Chen, C.R. Kao, Journal of Electronic Materials, 30 (2001) 379.

[4] A.M. Minor, J.W. Morris, Jr., Metallurgical and Materials Transactions A, 31 (2000) 798.

[5] K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano, K.N. Tu, Journal of Applied Physics, 97 (2005) 024508.

[6] R.-W. Yang, Y.-W. Chang, W.-C. Sung, C. Chen, Materials Chemistry and Physics, 134 (2012) 340.

[7] Y.-P. Su, C.-S. Wu, F.-Y. Ouyang, Journal of Electronic Materials, (2015) 1.

[8] W. Yang, R. Messler, L. Felton, Journal of Electronic Materials, 23 (1994) 765.

[9] H.-H. Hsu, S.-Y. Huang, T.-C. Chang, A.T. Wu, Applied Physics Letters, 99 (2011) 251913.

[10] R. Labie, W. Ruythooren, K. Baert, E. Beyne, B. Swinnen, in: (Eds), 2008 IEEE International Interconnect Technology Conference, IITC, 2008, 19.

[11] W. Yiwei, C. Seung-Hyun, R. Dunne, Y. Takahashi, K. Mawatari, P. Steinmann, T. Bonifield, J. Tengfei, J. Im, P.S. Ho, in: (Eds), Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 2012, 319.

[12] H.-Y. Hsiao, C.-M. Liu, H.-W. Lin, T.-C. Liu, C.-L. Lu, Y.-S. Huang, et al. Science 336 (2012) 1007.

[13]W.M. Chen , T.L Yang , C. K. Chung , C. R. Kao . Scripta Mater 65 (2011) 331.



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