Development in electronic packaging and their reliability concerns from metallurgical perspective: part II

As silicon technology continues to advance, engineers have opened up a third dimension (3D ICs) as a viable alternative to the limits of Moore’s law beyond 14 nm technology node. In 3D ICs, TSVs (through silicon vias) are critical elements made of pure copper connecting a multiple stack of dies vertically (Fig below). However, the thermal mismatch between copper and silicon exposes complex stresses in TSV as well as silicon surrounding TSVs leading to Cu extrusion, interfacial failure and performance degradation. In this post, I share with you what I have learnt about the world of TSVs from literature and from metallurgical perspective. I haven’t had the luxury of working in microelectronics industry yet so what it comes in the following is solely originated from my own passion for microelectronics and is rather a general viewpoint. In part I, metallurgy of micro-bumps is discussed.

 

img_1539-1
Fig. 1

Thermal cycling, the trouble-maker

In any physical system consisting of different materials with different thermal expansion coefficient (CTE), residual stresses are inevitable when the entire system is subjected to repeatedly fluctuating temperatures of extreme. Similarly, the mismatch of CTE between Si (CTE: 3ppm/K) and Cu (CTE:17 ppm/K) during processing and service where temperature fluctuates significantly leads to build up of stress in both materials. As a result, the residual stress in copper TSV can easily reach or go beyond its yield stress and this is when important reliability issues emerge.

TSV extrusion:

When temperature rises during processing or service, the rate at which copper expands is much higher than silicon leading to build up of compressive stress in copper TSVs. In response to this compressive stress, copper TSVs pop up at the top where they have the freedom to expand and release the induced stress. Different terms and acronyms created to address the height increase induced by residual stress in copper TSVs, such as “extrusion”, “intrusion”, “pop-up” or “pumping”. Though to prevent confusion, I stick to TSV extrusion in this post. TSV extrusion is in fact caused by plastic deformation of copper and does not go back to its original state when the temperature returns to room temperature.

TSV extrusion is schematically illustrated in Fig 2. The height increase generally is about several hundreds of nanometer which is quite detrimental to BEOL layers above TSVs. TSV extrusion can deform or crack the metal/dielectric stacks on the top, creating serious reliability concerns. In addition, the thermal mismatch of copper and silicon induces stress in silicon, as well, which can potentially influence FEOL, specifically in the region close to the TSV impacting transistors performance. Therefore, a keep-out-zone (KOZ) exists around TSVs to avoid this issue. KOZ is actually a zone free of any devices.

 In order for scientists and engineers to eliminate or lessen the complications associated with residual stresses in TSVs, it is very important that they obtain a systematic understanding of the underlying operating mechanisms in response to residual stress in TSVs. TSVs are made of copper, an FCC crystalline metal, which responses to stresses beyond yield stress based on metallurgical principals. On the other hand, TSVs are in contact with layers of different materials, consequently, interfacial principals have a role to play, as well. Therefore, the issue of TSVs reliability should be approached from two perspectives: 1-metallurgical and 2- interfacial.

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Fig. 2

 

Influence of microstructure on the reliability of TSVs

Generally, when we talk about metallurgy of TSVs in the context of reliability of 3D ICs, grain size and texture as well as impurities are the main factors of consideration. According to Hall-Petch effect, grain size determines the yield strength of a material so that the finer the grain size the stronger the material. Texture is also an important parameter as accumulation of stress within individual grains, as well as deformation mechanisms, can be orientation dependant. Impurities (or second phase particles) are another parameter that captures interest of reliability researchers. To find out the role of these parameters on the reliability of copper TSVs, we need to know about the mechanisms responsible for TSV extrusion, first.

The often discussed mechanisms underlying TSV extrusion are mainly the diffusion based mechanisms such as grain boundary sliding, coble-creep, grain boundary diffusion and lattice diffusion. Although it is not a surprise that at the presence of temperature (originating from BEOL and die-stacking processes or during service) and stress (originating from the thermal mismatch of constituent materials) these mechanisms are easily activated leading to TSV extrusion, preventing activation of these mechanisms entirely might not benefit reliability of TSVs. This is because the stress accumulated within the TSV has to be relaxed somehow and if we don’t allow it to relax through microstructure, it will relax through interface leading to cracks developing at the interface of TSV and barrier layers. Therefore rather than preventing these relaxation mechanisms entirely, the effort should be placed on engineering relaxation mechanisms so that minimum amount of damage occurs. Having said that, there are few researches backing up my above statement in which they have shown that playing with chemistry of electroplating and adding impurities to copper TSV does not benefit reliability issues [1,2]. This is because impurities pin grain boundaries and dislocations and decrease their mobility significantly. This might appear advantageous at first look as it prevents mechanisms responsible for extrusion, but in fact it potentially put the interfaces at a high risk of cracking.

The best possible approach to engineer these relaxation mechanisms could be through controlling grain size and texture. Classically, decreasing grain size increases the strength of metals, however, it should be noted that the easy path of diffusion is through grain boundaries. This means that smaller grain size works in favour of diffusion-based mechanisms. In other words, smaller grain sizes promote larger copper extrusion at the TSV top where there are more freedom for copper to expand in response to fluctuating temperatures and forming stress. Therefore, increasing grain size can technically appear much more beneficial in reducing TSV extrusion. This is consistent with the results of researchers from IMEC where they have shown that microstructure at TSV top in terms of grain size is instrumental and TSV top with single grain show significantly lower extrusion height if compared with TSV top with multiple grains [1,3].

In terms of texture, although there is not a direct correlation between texture and Copper extrusion reported in the literature yet, “bamboo structure” in which grain boundaries are aligned normal to TSV height can be an ideal structure to minimize TSV extrusions. “Bamboo structure” was first introduced to minimize electromigration in TSV copper [4]. The principal associated with “bamboo structure” is that grain boundaries are not directed to the top, therefore, the passages of electrons through grain boundaries to the top is minimised and so is electromigration damage. For the exact same reason, grain boundaries that are not directed to the top of TSV, can reduce diffusion of atoms to the top and consequent TSV extrusion.

Interfacial effects:

In addition to microstructure, Professor Dutta from Washington state university and his research group have done fair amount of research on the interface of TSVs with barrier layers (metallization and passivation layer) and its behaviour in response to residual stresses (for example [5-7]. Based on their work, interface of a metallic material with a non-metallic can be also prone to diffusion and sliding as it can provide an easy path for diffusion of atoms. Therefore similar to microstructure scenario, temperature and stress are driving flux of atoms at the interface (interfacial sliding) assisting the release of residual shear stresses at the interface. It is interesting to know that, interfacial sliding can lead to both TSV extrusion and intrusion depending on the initial state of stress in TSVs [6]. Also, they have investigated the role of electro-migration and found that electric current can enhance extrusion or intrusion if electron flux is in the direction of the shear stress. If not in the same direction, they then counteract each other [5].

[1] J. D. Messemaeker, O. V. Pedreira, H. Philipsen, E. Beyne, I. De Wolf, T. V. Donck & K. Croes, “Correlation between Cu Microstructure and TSV Cu Pumping”, proceeding- Electronic Components & Technology Conference, 2014, 613-619.

[2] T. Jiang et al. “Plasticity mechanism for copper extrusion in through-silicon vias for three- dimensional interconnects”, Applied Physics Letters, 2013, 103, 211906.

[3] I. De Wolf et al. “Cu pumping in TSVs: Effect of pre-CMP thermal budget”, Microelectronics Reliability, 2011, 51, 1856–1859.

[4] R. G. Filippi, J. A. Fitzsimmons,Kevin Kolvenbach, P.-C. Wang, “Electromigration immune through-substrate vias” 2011,US20110193199 A1.

[5] P. Kumar, I. Dutta, “Influence of electric current on diffusionally accommodated sliding at hetero-interfaces” Acta Materialia, 2011, 59, 2096–2108.

[6] P. Kumar, I. Dutta, M. S. Bakir, “Interfacial Effects During Thermal Cycling of Cu-Filled Through-Silicon Vias (TSV)”, Journal of Electronic Materials, 2012, 41, 322-335.

[7] I. Dutta, P. Kumar, M. S. Bakir “Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias”, JOM, 2011, 63, 70-77.

 

 

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