Development in electronic packaging and their reliability concerns from metallurgical perspective: part II

As silicon technology continues to advance, engineers have opened up a third dimension (3D ICs) as a viable alternative to the limits of Moore’s law beyond 14 nm technology node. In 3D ICs, TSVs (through silicon vias) are critical elements made of pure copper connecting a multiple stack of dies vertically (Fig below). However, the thermal mismatch between copper and silicon exposes complex stresses in TSV as well as silicon surrounding TSVs leading to Cu extrusion, interfacial failure and performance degradation. In this post, I share with you what I have learnt about the world of TSVs from literature and from metallurgical perspective. I haven’t had the luxury of working in microelectronics industry yet so what it comes in the following is solely originated from my own passion for microelectronics and is rather a general viewpoint. In part I, metallurgy of micro-bumps is discussed.

 

img_1539-1
Fig. 1

Thermal cycling, the trouble-maker

In any physical system consisting of different materials with different thermal expansion coefficient (CTE), residual stresses are inevitable when the entire system is subjected to repeatedly fluctuating temperatures of extreme. Similarly, the mismatch of CTE between Si (CTE: 3ppm/K) and Cu (CTE:17 ppm/K) during processing and service where temperature fluctuates significantly leads to build up of stress in both materials. As a result, the residual stress in copper TSV can easily reach or go beyond its yield stress and this is when important reliability issues emerge.

TSV extrusion:

When temperature rises during processing or service, the rate at which copper expands is much higher than silicon leading to build up of compressive stress in copper TSVs. In response to this compressive stress, copper TSVs pop up at the top where they have the freedom to expand and release the induced stress. Different terms and acronyms created to address the height increase induced by residual stress in copper TSVs, such as “extrusion”, “intrusion”, “pop-up” or “pumping”. Though to prevent confusion, I stick to TSV extrusion in this post. TSV extrusion is in fact caused by plastic deformation of copper and does not go back to its original state when the temperature returns to room temperature.

TSV extrusion is schematically illustrated in Fig 2. The height increase generally is about several hundreds of nanometer which is quite detrimental to BEOL layers above TSVs. TSV extrusion can deform or crack the metal/dielectric stacks on the top, creating serious reliability concerns. In addition, the thermal mismatch of copper and silicon induces stress in silicon, as well, which can potentially influence FEOL, specifically in the region close to the TSV impacting transistors performance. Therefore, a keep-out-zone (KOZ) exists around TSVs to avoid this issue. KOZ is actually a zone free of any devices.

 In order for scientists and engineers to eliminate or lessen the complications associated with residual stresses in TSVs, it is very important that they obtain a systematic understanding of the underlying operating mechanisms in response to residual stress in TSVs. TSVs are made of copper, an FCC crystalline metal, which responses to stresses beyond yield stress based on metallurgical principals. On the other hand, TSVs are in contact with layers of different materials, consequently, interfacial principals have a role to play, as well. Therefore, the issue of TSVs reliability should be approached from two perspectives: 1-metallurgical and 2- interfacial.

img_1542-1
Fig. 2

 

Influence of microstructure on the reliability of TSVs

Generally, when we talk about metallurgy of TSVs in the context of reliability of 3D ICs, grain size and texture as well as impurities are the main factors of consideration. According to Hall-Petch effect, grain size determines the yield strength of a material so that the finer the grain size the stronger the material. Texture is also an important parameter as accumulation of stress within individual grains, as well as deformation mechanisms, can be orientation dependant. Impurities (or second phase particles) are another parameter that captures interest of reliability researchers. To find out the role of these parameters on the reliability of copper TSVs, we need to know about the mechanisms responsible for TSV extrusion, first.

The often discussed mechanisms underlying TSV extrusion are mainly the diffusion based mechanisms such as grain boundary sliding, coble-creep, grain boundary diffusion and lattice diffusion. Although it is not a surprise that at the presence of temperature (originating from BEOL and die-stacking processes or during service) and stress (originating from the thermal mismatch of constituent materials) these mechanisms are easily activated leading to TSV extrusion, preventing activation of these mechanisms entirely might not benefit reliability of TSVs. This is because the stress accumulated within the TSV has to be relaxed somehow and if we don’t allow it to relax through microstructure, it will relax through interface leading to cracks developing at the interface of TSV and barrier layers. Therefore rather than preventing these relaxation mechanisms entirely, the effort should be placed on engineering relaxation mechanisms so that minimum amount of damage occurs. Having said that, there are few researches backing up my above statement in which they have shown that playing with chemistry of electroplating and adding impurities to copper TSV does not benefit reliability issues [1,2]. This is because impurities pin grain boundaries and dislocations and decrease their mobility significantly. This might appear advantageous at first look as it prevents mechanisms responsible for extrusion, but in fact it potentially put the interfaces at a high risk of cracking.

The best possible approach to engineer these relaxation mechanisms could be through controlling grain size and texture. Classically, decreasing grain size increases the strength of metals, however, it should be noted that the easy path of diffusion is through grain boundaries. This means that smaller grain size works in favour of diffusion-based mechanisms. In other words, smaller grain sizes promote larger copper extrusion at the TSV top where there are more freedom for copper to expand in response to fluctuating temperatures and forming stress. Therefore, increasing grain size can technically appear much more beneficial in reducing TSV extrusion. This is consistent with the results of researchers from IMEC where they have shown that microstructure at TSV top in terms of grain size is instrumental and TSV top with single grain show significantly lower extrusion height if compared with TSV top with multiple grains [1,3].

In terms of texture, although there is not a direct correlation between texture and Copper extrusion reported in the literature yet, “bamboo structure” in which grain boundaries are aligned normal to TSV height can be an ideal structure to minimize TSV extrusions. “Bamboo structure” was first introduced to minimize electromigration in TSV copper [4]. The principal associated with “bamboo structure” is that grain boundaries are not directed to the top, therefore, the passages of electrons through grain boundaries to the top is minimised and so is electromigration damage. For the exact same reason, grain boundaries that are not directed to the top of TSV, can reduce diffusion of atoms to the top and consequent TSV extrusion.

Interfacial effects:

In addition to microstructure, Professor Dutta from Washington state university and his research group have done fair amount of research on the interface of TSVs with barrier layers (metallization and passivation layer) and its behaviour in response to residual stresses (for example [5-7]. Based on their work, interface of a metallic material with a non-metallic can be also prone to diffusion and sliding as it can provide an easy path for diffusion of atoms. Therefore similar to microstructure scenario, temperature and stress are driving flux of atoms at the interface (interfacial sliding) assisting the release of residual shear stresses at the interface. It is interesting to know that, interfacial sliding can lead to both TSV extrusion and intrusion depending on the initial state of stress in TSVs [6]. Also, they have investigated the role of electro-migration and found that electric current can enhance extrusion or intrusion if electron flux is in the direction of the shear stress. If not in the same direction, they then counteract each other [5].

[1] J. D. Messemaeker, O. V. Pedreira, H. Philipsen, E. Beyne, I. De Wolf, T. V. Donck & K. Croes, “Correlation between Cu Microstructure and TSV Cu Pumping”, proceeding- Electronic Components & Technology Conference, 2014, 613-619.

[2] T. Jiang et al. “Plasticity mechanism for copper extrusion in through-silicon vias for three- dimensional interconnects”, Applied Physics Letters, 2013, 103, 211906.

[3] I. De Wolf et al. “Cu pumping in TSVs: Effect of pre-CMP thermal budget”, Microelectronics Reliability, 2011, 51, 1856–1859.

[4] R. G. Filippi, J. A. Fitzsimmons,Kevin Kolvenbach, P.-C. Wang, “Electromigration immune through-substrate vias” 2011,US20110193199 A1.

[5] P. Kumar, I. Dutta, “Influence of electric current on diffusionally accommodated sliding at hetero-interfaces” Acta Materialia, 2011, 59, 2096–2108.

[6] P. Kumar, I. Dutta, M. S. Bakir, “Interfacial Effects During Thermal Cycling of Cu-Filled Through-Silicon Vias (TSV)”, Journal of Electronic Materials, 2012, 41, 322-335.

[7] I. Dutta, P. Kumar, M. S. Bakir “Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias”, JOM, 2011, 63, 70-77.

 

 

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Development in electronic packaging and their reliability concerns from metallurgical perspective: part I

Introduction

If you are interested in microelectronics industry and are following the latest trends, you have heard the buzz about internet of things (IoT) and wearable technology. Although the concept might not be new, the advances in microelectronics now allow smooth adoption of the technology, revolutionizing human’s life once again after the arrival of internet. In this regard, advanced electronic packaging is a key component to successful integration of IoT and wearable technology. Generally, the essence in advanced electronic packaging is integrating multifunctional modules (logic, memory, RF, sensors, etc.) based on 3D integration. 3D integrated circuits (3D ICs) requires an increased Input/Output densities, stacking chips and interconnecting vertically by through silicon via (TSV) technology providing high performance, low power and reliable electronics. However to the best of my knowledge, moving toward 3D ICs does not exempt from complications and a lot of effort is going on in the industry to overcome those complications. Many of these challenges originates from the fact that despite significant experience of industry in 2D flip chip packaging technology, many of those experiences are not transferable to 3D packaging. This is while as the chip technology is approaching the limits of Moore’s law, moving to 3D ICs seems inevitable as it offers ample room for further growth of electronic industry for at least the next 15-20 years.

Generally, a chip contains different metallic components and understanding metallurgical principles governing the behavior and reliability of these components appears vital to further development of the technology. In metallurgical science, size effect is always a concern as reducing the size (of grains, thickness, precipitates, etc) below a certain amount can potentially alter the governing metallurgical principles. For instance, when the grain size is reduced to the range of nanometers dislocation mediated mechanisms will be largely replaced by grain boundary mediated mechanisms. These change of mechanisms are the origin of complications associated with materials behavior when reducing size is inevitable.  As already mentioned, the new trend in electronic packaging is all about miniaturising and reducing sizes.  Likewise, the well-known metallurgical principles which formed the foundation of reliability experience of the industry for years , changes with this emerging trend of miniaturizing and a new level of understanding is required to keep up with the demand of the market. As an example of this, moving from 2D ICs to 3D ICs requires a significant reduction in the size of bumps to the range of so-called micro-bumps. This continuous reduction in size of bumps can eventually reach to the point where each micro-bump contains only one single grain leading to a significant inhomogeneous behavior across the entire 3D ICs, as each single grain can respond to its environment differently based on its orientation.   In this (and following) post, thus, I aim to provide an overview of the current trend in electronic packaging and relevant reliability issues from metallurgical perspective.

 

TSV and Micro-bumps the main metallic (and the most mischievous) components of 3D ICs

More dense, high performance 3D ICs requires an increasing number of Inputs/Outputs (IOs) obtained through scaling down to fine pitch and micro-bumps less than 50 micron and stacking multifunctional chips (such as logic, memory, RF and MEMS) using TSV interconnect. TSV interconnect are copper vias in polycrystalline form vertically passing through chips providing connection between chips. TSVs are created through a process of etching and electroplating. In this process through holes are etched which are then filled with electroplated copper. The main advantage of TSV is the reduced travel length of signal from one layer to another, allowing an increased interconnect density, therefore increased functionality and performance. The connection between vertical vias in different layer is made through micro-bump technology. Micro-bumps are created by means of electroplating process. As mentioned earlier, due to the compact nature of 3D IC, micro-bumps used in this technology are much smaller than the conventional bump size used in 2D packaging. The thermal mismatch of the components (e.g. difference in coefficient of thermal expansion of TSV copper and silicon) and the small size of micro-bumps leads to some unique characteristics that can create some critical reliability issues (when I was first learning about micro-bumps and TSVs, the first thing that passed my mind was how mischievous these components are as I never knew how much trouble they can create in advanced electronic packaging). In what follows in this part, I try to cover micro-bumps and their reliability concerns briefly and TSVs will be reviewed in a separate post. Please keep in mind that the universe of metallurgy of microelectronics is vast and what is provided here is just a brief summary of the literature.

 

Microbumps and Intermetallic Compounds Formation

Soldering is the essential part of interconnection technology and obviously will remain so in the future. By definition, soldering is the chemical reaction between the solder alloy and the two surfaces to be joined together. Since 2006, the consumer electronic market has fully transferred to Pb-free solder alloys due to the health and environmental concerns associated with Pb-Sn solder alloys. Replacement of Pb-Sn was initially appeared possible through a near eutectic Sn-Ag-Cu or SAC alloy. However, development of SAC alloys did not lead to a stop to further alloy developments and there has been continuous effort to develop solder alloys for a wide range of applications. Nevertheless, since near eutectic SAC alloy is the most common solder alloy currently and it is believed that it will remain to be the major candidate for 3D ICs, at least in the near future, the information is provided in this post is mainly based on this alloy.

Generally, an interconnect system consists of solder bumps in contact with under bump metallurgy system or UBM. UBM to interconnection technology is like a foundation to a house providing support to the whole system. UBM contains different metallic layers (or thin films) each playing different role. In case of SAC solder alloy, the UBM is composed of a Cu layer as solder adhesion layer, Ni layer as the diffusion barrier layer and Au layer as the oxidizing barrier layer. Cu, Ni, Ag, and Au are known as fast diffusers meaning that their diffusion rate in body centred tetragonal Sn is orders of magnitude higher than self-diffusion rate of Sn [1]. Therefore, the interfacial chemical reaction between solder and UMB leads to formation of IMCs which is on one hand an indication of a good metallurgical bonding, but on the other hand IMCs are brittle in nature and prone to structural defects which can undermine the reliability of solder joints.

The intermetallic product of reaction between solder alloy and UBM varies depending on the solder alloy composition, UBM layer components, UBM layer thickness and kinetics of reaction. In a binary system possible alternatives of IMCs are as follow: Cu6Sn5, Ni3Sn4 and AuSn4. However, through multiple reflow and subsequent aging treatment Cu3Sn [2] and other alternatives of ternary and quaternary IMCs appears in the solder [3, 4]. Cu3Sn formation is accompanied by Kirkendall voids formation, a phenomena resulted from the difference between the diffusion rates of Cu and Sn which promotes voids formation and eventually crack formation at the interface of Cu3Sn and Cu [5].

In the conventional flip chip with bump sizes of larger than 50μm, IMCs can form both as a thin layer at the interface and as particles distributed in the matrix of solder depending on the type of IMCs formed. A thin layer of IMC at the interface provides a good bonding and dispersed IMC particles in the matrix can improve mechanical properties of the joints. However in 3D IC technology with the micro-bump size requirements in the range of a few micrometers, solder alloy can potentially turn fully into IMCs that  is not regarded beneficial in terms of mechanical properties of the joints (due to their brittle nature). Another example of complications associated with the small volume of micro-bumps is formation of Ag3Sn (another form of IMCs).  While Ag3Sn does not seem to be much of a concern in conventional flip chip bump sizes, it can create serious reliability concerns in micro-bumps [6, 7]. The reason for formation of Ag3Sn in microbumps originates from the low volume of solder alloy in micro-bump. Rapid initial consumption of Sn by IMC formation leads to an increase in concentration of Ag which in turn promotes Ag3Sn formation [6].

Other than being brittle, different IMCs have different thermal expansion leading to formation and propagation of voids at the interface of IMCs in the subsequent aging treatments [8, 9]. Similar to Kirkendall voids, these voids can lead to crack propagation and early failure of the interconnect thereby, creating a significant reliability issue in micro-bumps where a large fraction of solder alloy transforms to IMCs.

As a large fraction of micro-bumos turn into IMCs during subsequent thermal treatment, It should be ,therefore, noted that the reliability standards developed for conventional flip chip bumps could not be transferred to micro-bumps as the reliability of the former is dominated by properties of βSn while the latter is dominated by IMCs. Surely, developing new reliability standards is an exciting field of work from my perspective as a scientist but a tough challenge for industry in the effort to track I/O roadmap.

 

Micro-bumps and Electromigrations

Electromigration (EM) refers to the mass transport of atoms under applying current density in metals. The flux of atoms in the direction of electron flow leads to fast dissolution of UBM and voids/hillocks formation at the interface of joint and UBM. The former increase the rate of IMCs formation and the latter leads to an increase in current crowding effect and further elevating EM. Extensive IMC formation and voids at the interface can create localized stress concentration while in service resulting in early failure of electronic components and devices.

The smaller size of micro-bumps results in substantial increase of current density flowing through the joints based on this relation:

J=I/A

Where J is the current density, I is the current and A the area. For example, applying a current of 0.05A on a 20μm-microbump results in a value in order of 104A/cm. Increasing current density increases the transport of Cu, Ni, Au and Ag atoms driven by electron current. Additionally, increasing current density leads to a local increase of joint temperature as Joule heating is proportional to the square of current density. Also, field service temperature can reach as high as 100 °C, approximately 76% of the melting temperatures of SAC alloy. High current density and high temperature in the micro-bumps, therefore, promotes the flux of atoms and increase the diffusion rate in the direction of electron flow. Consequently, EM could be significantly pronounced reliability issue in 3D ICs technology with an enhanced rate of IMCs and Kirkendall voids formation, if compared with conventional flip chip technology under the same applying current. However, it is interesting to note that there are evidence of an improved resistance to EM in 3D ICs and that is attributed to fact that IMCs have an enhanced resistance to EM in comparison with the solder alloy [10, 11]. Once the solder alloy transformed fully or largely to IMCs, therefore, a drop in EM rate is expected.

 

Micro-bumps and microstructural anisotropy

Micro-bumps can have dimensions one to two orders of magnitude smaller than the conventional bumps in the flip-chip technology. This significant reduction in dimension may result in micro-bump having only one grain. As Sn has a body-centered tetragonal crystal structure, its properties (e.g. conductivity) is anisotropic. Even when micro-bumps are fully consumed by ICs, not much changes are expected in terms of isotropic properties as crystalline structure of ICs are mainly anisotropic, as well [12,13]. This would be a serious reliability concern when there are a large number of micro-bumps.

References

[1] M. Lu, D.-Y. Shih, P. Lauro, C. Goldsmith, D.W. Henderson, Applied Physics Letters, 92 (2008) 211909.

[2] T. Laurila, V. Vuorinen, J.K. Kivilahti, Materials Science and Engineering R: Reports, 49 (2005) 1.

[3] C.E. Ho, W.T. Chen, C.R. Kao, Journal of Electronic Materials, 30 (2001) 379.

[4] A.M. Minor, J.W. Morris, Jr., Metallurgical and Materials Transactions A, 31 (2000) 798.

[5] K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano, K.N. Tu, Journal of Applied Physics, 97 (2005) 024508.

[6] R.-W. Yang, Y.-W. Chang, W.-C. Sung, C. Chen, Materials Chemistry and Physics, 134 (2012) 340.

[7] Y.-P. Su, C.-S. Wu, F.-Y. Ouyang, Journal of Electronic Materials, (2015) 1.

[8] W. Yang, R. Messler, L. Felton, Journal of Electronic Materials, 23 (1994) 765.

[9] H.-H. Hsu, S.-Y. Huang, T.-C. Chang, A.T. Wu, Applied Physics Letters, 99 (2011) 251913.

[10] R. Labie, W. Ruythooren, K. Baert, E. Beyne, B. Swinnen, in: (Eds), 2008 IEEE International Interconnect Technology Conference, IITC, 2008, 19.

[11] W. Yiwei, C. Seung-Hyun, R. Dunne, Y. Takahashi, K. Mawatari, P. Steinmann, T. Bonifield, J. Tengfei, J. Im, P.S. Ho, in: (Eds), Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, 2012, 319.

[12] H.-Y. Hsiao, C.-M. Liu, H.-W. Lin, T.-C. Liu, C.-L. Lu, Y.-S. Huang, et al. Science 336 (2012) 1007.

[13]W.M. Chen , T.L Yang , C. K. Chung , C. R. Kao . Scripta Mater 65 (2011) 331.

 

Adaptable nature of Moore’s law through materials engineering

As mentioned briefly in my previous post, Moore’s law is not merely about the number of transistors integrated into a small chip. It is generally about strategies to decrease the processing time, power consumption, weight and cost (have a look at the new Skylake processor for example). Although with the recent IBM’s announcement of 7nm chip technology, increasing computing power through increasing transistors count still seem to be the main preference for industries, they have been continuously looking into alternatives as the current silicon technology is approaching its limits. In bypassing those limits, materials engineering has done a great deal of benefit and will continue to play a significant role in the future. In what follows, I will go briefly through materials engineering related strategies applied to keep up the pace of development Moore predicted 50 years ago.

Copper interconnect

Late 90s was the time when microelectronic industries realised the urge for switching from aluminium to copper interconnect. This was basically due to higher conductivity of copper compared to aluminium leading to less power consumption and smaller metallic components. Additionally, higher resistance of copper to electromigration  was another advantage which appeared attractive to the industry. Electromigration is a phenomenon through which mass of atoms are misplaced due to collision of the current conduction electrons with the atoms. This misplacement of atoms is highly undesirable in terms of reliability of electronic devices. Material chemistry and microstructure of material such as grain size and orientation can play a significant role in electromigration of atoms.  However apart from metallurgical factors, current density is a major role player and it can highly aggravate the effect of electromigration. As the current density in the interconnect is high enough to aggravate electromigration, therefore it is a serious reliability problem and copper has remained the metal of choice for interconnect materials.

High-K materials

Gate leakage in semiconductor devices is a quantum mechanics phenomenon through which mobile charge carriers tunnel through an insulating barrier. Gate leakage is very sensitive to the thickness of insulating barriers and obviously highly undesirable as it reduces the processor performance quite significantly. Minimizing leakage is necessary to facilitate miniaturization of electronic devices and one way to reduce leakage could be increasing thickness, however, it should be noted that increasing physical thickness which leads to an increased electrical thickness is not an option as it deteriorates transistors performance. Apart from proper system design which I don’t want to go through that here, it appeared that with a proper selection of materials it is possible to further down scale the electrical thickness while providing a physically thicker layer, achieved by replacing silicon dioxide with high dielectric constant metal oxides (so called high-k dielectric).  Hafnium-based dielectric layer in combination with a gate electrode composed of alternative metal materials was Intel’s ingredient  for fabrication of 45 nm microprocessors in 2007 and the following down scaling of transistors beyond 45 nm.

Strained Silicon

Another way to improve the performance of transistors and speed up the processing time is increasing the electron mobility through changing silicon properties. Stretching atoms of silicon beyond their normal interatomic distance decreases the forces that interfere with the movement of electrons leading to a boost in the performance of a transistor. Strained silicon technology is currently using the same concept to increase the electron mobility of silicon which is done through depositing a layer of silicon on the top of silicon-germanium layer. Due to a mismatch between the atoms of silicon layer and silicon-germanium layer, the atoms of silicon are stretched. The force stretched atoms apply on the moving electrons is reduced notably, thereby enhancing electron mobility of silicon compared with normal bulk silicon crystal.

Materials with higher electron mobility than silicon

In my twitter feed yesterday there was an announcement from Intel regarding its new $50M investment in quantum computing. Whenever I hear about quantum computing, the first thing that comes automatically to my mind as a materials engineer is the destiny of current established and future developing materials (for the purpose of computing) with the advent of quantum computing.  I have not done much research into quantum computing yet but up to my limited understanding, silicon’s related limitations does not apply in quantum computing. This means that with quantum computing silicon would remain material of choice without the requirement of replacing it with new exotic materials. However, it seems that quantum computing has got a long way to go and replacing silicon seem to be a more tangible option to catch up with Moore’s prediction.

For instance, a new family of semiconductors, so called  compound semiconductors (they are composed of two or more elements such as indium arsenide and indium antimonide), have electron mobility up to 50 times higher than silicon and their application is in the rise.  In addition, adding a small amount of germanium to silicon can enhance its electron mobility properties and this approach is also  in use already. It is interesting to note that very first semiconductor devices were made of germanium so moving back to a fully germanium chip could be a possible option. Moreover, hybrid semiconductors in which different materials are combined could be a real life possibility anytime soon.

Graphene or the “miracle material” has been attracting a lot of attention recently as a possible alternative to silicon due to its extraordinary properties such as remarkable strength, thermal and electrical conductivity. In its current form however, graphene is not viable as a semiconductor material because it lacks a band gap which is a requirement for semiconducting properties. If the issue of lack of band gap is resolved, then graphene could be a promising future material for further development of electronic devices. Carbone nanotube is another form of graphene (rolled graphene) which holds promises as possible future material for microelectronic industry. Similarly, it has extraordinary properties in terms of strength, electrical and thermal conductivity, however, the current challenges with manufacturing of carbon nanotube such as control over diameter, density and chirality remain the main barrier against its commercial applications.

moving up from chip level to assembly of components level, there are still more room for materials engineering and specifically metallurgy to play a role in keeping up with Moore’s prediction – which I will go through that in a separate post. Stay tuned!

Moore’s Law

Moore’s law has obviously nothing to do with metallurgical science but as I have dedicated this section to the role of metallurgical science in microelectronics, I thought it is worth to go through Moore’s law briefly before anything else as it is the foundation of the current high-tech advancement.

Moore’s law was initially introduced in 1965 by Gordon E. Moore, the co-founder of the Intel Corporation and Fairchild Semiconductor, through which he predicted that the number of transistors on an integrated circuit double every two years. This means faster processing speed and smaller / lighter electronic devices over every few year time period (compare the first portable computer Osborne 1 weighing around 23 pounds and 64 KB of main memory to your smartphone right now in your hand with various functions and a possible capacity of 128 GB storage). In other words, Moore’s prediction is the basis of all amazing advancement in the last 50 years by setting the destination for microelectronic industry. To put this in perspective, imagine applying  Moore’s law to automotive industry, then now we would have cars with the capacity of 300000 miles/hour, 2000000 miles/gallon and all for the price of only 4 cents. Moore’s law not only has set the pace at which semiconductor industry develop, but also it has shaped the world we are living in today. It is the foundation of Moore’s law that is driving the way we communicate, work, study and entertain today.

However, concerns are raising  in regards to the limits of Moore’s law as we are now literally approaching those limits. The concerns stem from the fact that transistors cannot get smaller than a few nanometres physically and technically and this is where it is argued to be the limits of Moore’s law and consequently end of an era. Though, a review of research literature and industrial trend make it clear that Moore’s prediction is far beyond the number of transistors on an integrated circuit. In more general terms, it is about approaches to increase the computing power and reducing cost and if one approach is reaching its limit, other approaches will be developed. Even the recent trend of “More than Moore” (MtM) is a direct consequence of Moore’s prediction and it is not detachable from Moor’s law by nature. Currently, it appears that microelectronic industry have a high spirit to keep up the pace and I strongly believe that Moore’s law will continue to revolutionize human life with the same speed if not higher in the next decades. Best is yet to come.

Metallurgy meets Microelectronics

Have you ever inspected inside of any electronic devices? If so, you might have noticed a green board similar to the one shown in the picture with a lot of components and chips being connected to it and to each other via wires and solder bumps, etc. At first look, you might think that those connections and circuits and chips are all about electronics and electrical engineering. But in reality, multiple disciplines of engineering have to come together to make the final product function as required and metallurgy is surely one of those disciplines.

pcb

an example of printed circuit board, photo via wikimedia commons

When it comes to the reliability and performance of our electronic devices, interconnect system is a major role player. It is the job of the interconnect system to keep components in place in addition to transmitting electronic signals. Moreover, heat generation is inevitable while transmitting electronic signals. Therefore, the interconnect system has to provide heat dissipation function as well. With such critical roles to play, hence, one can conclude that a reliable functioning of our electronic devices largely depends on the interconnect system. If one component gets disconnected it can create disaster and paralyse the entire system. Providing mechanical and thermal support in addition to signal transmission however has got its route in physical and mechanical metallurgy of the interconnect materials and this is where metallurgy intervene. So watch this space if you are interested to find out more.